The present invention relates to memory systems; more particularly, the present invention relates to levelizing memory devices in different time domains on a Rambus channel.
The Rambus Dynamic RAM (RDRAM) developed by Rambus, Inc., of Mountain View, Calif., is a type of memory that permits data transfer operations at speeds up to 1.2-1.6 gigabytes per second. RDRAM chips are housed in Rambus in-line memory modules (RIMMs) that are coupled to one or more Rambus channels. Typically, the expansion channels couple each RDRAM chip to a memory controller. The memory controller enables other devices, such as a Central Processing Unit (CPU), to access the RDRAMs.
Often the RDRAMs on a channel are located in different time domains. Time domains result from a skew at a memory device resulting from the time it takes a clock pulse to travel to and from a memory controller from a RDRAM. The skew for each RDRAM on an expansion channel is different. For instance, an RDRAM on an expansion channel that is close to the memory controller may have a very small skew, while an RDRAM further away from the memory controller may have a large skew.
Once the skew for a RDRAM exceeds a one clock period, the skew comes back in phase at a 360xc2x0 shift. A new time domain is created each time the clock skew goes through a 360xc2x0 cycle. The problem with having RDRAMs in different time domains is that the memory controller perceives the RDRAMs in later time domains to be slower. For example, if a RDRAM is one time domain behind the RDRAM closest to the memory controller it is perceived to be one clock cycle slower than the closest RDRAM.
In order to solve the problem of having RDRAMs in multiple time domains, RDRAMs that are located closer to the controller add appropriate delay such that they are perceived by the controller as being as slow as the furthest RDRAM. In an expansion channel with time domains 0, 1 and 2 for example, RDRAMs in time domain 0 must incur a two level delay and RDRAMs in time domain 1 must incur a one level delay. The RDRAMs are delayed by programming a configuration register within the requisite RDRAMs upon system 100 startup.
The process of determining how many time domains exist, where the boundaries between them are and programming the appropriate delay in the RDRAMs is referred to as levelization. Typically, the time domains on a channel are difficult to ascertain. Therefore, a mechanism for automatically determining the number of time domains on a channel is desired.
According to one embodiment, a computer system is disclosed. The computer system includes a memory controller, a first Rambus channel coupled to the memory controller and a memory system coupled to the first Rambus channel. The memory system is adaptable to determine the number of time domains on the first Rambus channel.